1. Field of the Invention
The invention relates to the fabrication of semiconductor devices, including integrated circuits, and more particularly, to a silicide structure and a process for forming silicides.
2. Description of Related Art
As integrated circuit geometries shrink, the forming of discreet devices on a semiconductor substrate becomes more specialized. Specialized deposition and etching techniques permit the density of semiconductor elements on a chip to greatly increase by minimizing the feature size of individual devices. The increased density translates into larger memory, faster operating speeds, and reduced production costs.
A typical metal oxide semiconductor (MOS) transistor generally includes source/drain diffusion regions in a substrate, and a gate electrode formed above the substrate between the diffusion regions and separated from the substrate by a relatively thin dielectric layer or gate oxide. Contact structures can be inserted to the diffusion regions and interlays can overly the contact structures and connect neighboring contact structures. These contact structures to the diffusion region are isolated from the adjacent gate by dielectric spacer or shoulder portions along the side portions of the gate. The dielectric spacer or shoulder portions also isolate the gate from the diffusion region.
FIG. 1 illustrates a planar side portion of a MOS integrated circuit. In FIG. 1, isolation areas or field oxides 160 separate active areas of semiconductor substrate 100. The active area includes a p- or n-type semiconductor substrate 100 underlying a gate 110 consisting of a polycrystalline silicon (polysilicon) line 130 overlying a gate oxide 120. Embedded in the substrate 100 are diffusion regions 150 (i.e., source/drain regions), that are heavily doped with the opposite dopant type of the substrate.
As the feature size of integrated circuits shrink to 0.5 .mu.m or less, the necessity of decreasing the resistance and capacitance associated with interconnection paths becomes more important. The higher the value of the interconnect resistance (R)x capacitance (C) product, the more likely it is the circuit operating speed will be limited by the RC delay. Thus, low resistivity interconnection paths are critical in order to fabricate dense, high performance devices. This is particularly true for MOS devices, in which the RC delay due to the interconnect paths can exceed the delays due to gate switching. Thus, efforts have been made to reduce the resistivity of the interconnect to less than the 15-300 ohm/sq typically exhibited by polysilicon.
The most common approach to reduce the resistivity of the interconnect to less than that exhibited by polysilicon alone is to form a multilayer structure, consisting of a low resistance material, e.g., a refractory metal silicide, on top of a doped polysilicon layer. Such a structure is termed a polycide. The advantages of the polycide gate/interconnect structure to replace polysilicon is that the known work function of polysilicon and the highly reliable polysilicon/SiO.sub.2 interface are preserved as polysilicon is still directly on top of the gate oxide.
As the dimensions of a device shrink, the contact resistance of the shallower junctions or diffusion regions also increases. To reduce these resistance values, while simultaneously reducing the interconnect resistance of the polysilicon lines, self-aligned or "silicide" technology is used. Salicide technology involves depositing metal over a MOS structure and reacting exposed silicon areas of the diffusion region as well as exposed polysilicon areas on the gate to form silicides.
A salicide structure is shown in FIGS. 1 and 2. FIG. 1 illustrates a planar side view of a portion of an integrated circuit. FIG. 2 illustrates a planar top view of a portion of the integrated circuit structure of FIG. 1. FIGS. 1 and 2 show active regions containing a silicided gate 110 and silicided diffusion regions 150. The gates 110 are separated from the diffusion regions by spacer portions 140.
The sidewall spacers 140 along the gate are used to prevent the gate 110 and diffusion regions 150 from being electrically connected by avoiding silicide formation on the spacer 140. The sidewall spacers 140 separate the diffusion regions 150 from the gate 110 by only about 500-3,000 .ANG.. Thus, any lateral formation of silicide can easily bridge this separation and cause the gate 110 to be shorted to the diffusion region 150.
The thickness of the silicide layer 135 in the gate 110 and the diffusion region 150 is approximately the same. This is because the thickness of the silicide layer 135 depends on the amount of as-deposited metal that reacts with exposed silicon. The general rule for improved sheet resistance is that the maximum thickness of the silicide layer is equal to one half of the junction depth of the diffusion region 150. Thus, for a diffusion junction 150 with a depth of 1,000 .ANG., the silicide depth in both the junction 150 and the gate 110 is approximately 500 .ANG.. As the devices become smaller, the line widths become narrower and the junctions become shallower. The shallower junctions limit the thickness of the silicide layer. However, the thickness of the silicide layer is inversely proportional to the sheet resistance. Thus, a thinner silicide layer means more resistance and a longer RC delay (i.e., a slower device).